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W9320 ADPCM CODEC
Table of Contents1. GENERAL DESCRIPTION.............................................................................................................................2 2. FEATURES ...................................................................................................................................................2 3. PIN CONFIGURATION..................................................................................................................................3 4. PIN DESCRIPTIONS .....................................................................................................................................3 4.1. Power Control Interface .........................................................................................................................3 4.2. Analog Interface ....................................................................................................................................4 4.3. ADPCM/PCM Serial Interface ................................................................................................................5 4.4 Serial Setup Port(SSP) Interface ............................................................................................................5 5. SYSTEM DIAGRAM ......................................................................................................................................6 5.1 Pair Gain System ...................................................................................................................................6 5.2. Cordless Phone System ........................................................................................................................7 6. BLOCK DIAGRAM.........................................................................................................................................8 7. FUNCTIONAL DESCRIPTIONS.....................................................................................................................8 7.1. Power Supply Management System ......................................................................................................8 7.2. Codec-Filter .....................................................................................................................................9 7.3. DSP Engine ..........................................................................................................................................9 7.4. Serial Setup Port (SSP).......................................................................................................................12 7.5. Sequence and Control .........................................................................................................................14 7.6. I/O Level .............................................................................................................................................14 8. CONTROL AND STATUS REGISTERS .......................................................................................................15 8.1. Introduction .........................................................................................................................................15 8.2. Byte Register Description ....................................................................................................................15 9. ELECTRICAL CHARACTERISTICS .............................................................................................................24 9.1. Absolute Maximum Ratings .................................................................................................................24 9.2. DC Characteristics ..............................................................................................................................24 9.3. Analog Transmission Characteristics...................................................................................................25 9.4. Analog Electrical Characteristics .........................................................................................................26 9.5. Digital Switching Characteristics..........................................................................................................27 10. APPLICATION INFORMATION..................................................................................................................30 10.1. Handset Application for Wireless Communication..............................................................................30 10.2. Transformer Application for Public Switching Telephone Network (PSTN) ..........................................30 11. HOW TO PROGRAM THE TONE GENERATOR .......................................................................................31 11.1 Introduction ........................................................................................................................................31 11.2 Tone Frequency Coefficient Calculation ..............................................................................................32 11.3 Tone Attenuation Coefficient Calculation.............................................................................................32 11.4 Frequency Coefficients for the DTMF Signal .......................................................................................32 12. PACKAGE DIMENSIONS ..........................................................................................................................33
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Publication Release Date: August 1997 Revision A1
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1. GENERAL DESCRIPTION
The Winbond ADPCM Codec is a single channel chip incorporating a PCM codec filter with a 32K, 24K, 16K ADPCM encoder/decoder complying with the CCITT G.721 and G.726 standards. In addition, this chip also meets the PCM conformance specification of the CCITT G.714 recommendation. This chip allows full-duplex operation over a wide voltage range from 2.7 to 5.25 volts; it's low power consumption makes it ideal for battery or AC powered applications. The chip includes a serial setup port (SSP) interface with a 16 byte setup and status registers. A microcontroller can access many built-in features through the SSP interface. In addition, this chip also consists of some OP amplifiers integrated with a PCM codec-filter to allow for easy control of the analog interface. This chip can be used on two key applications. One application is for wireless telephone systems such as CT2, DECT. Another application is for public switch telephone network (PSTN) applications such as pair gain. See the section on application information for more details.
2. FEATURES
* Single 2.7 to 5.25 volt power supply * Master clock rate: 10.24 MHz oscillator typically or 16.384 MHz for Winbond cordless system * Full-duplex single channel speech codec * Linear 14 bit PCM codec-filter for A/D and D/A converter * Complete Mu-Law and A-Law companding * ADPCM transcoder for 64, 32, 24, and 16 Kbps bit rates * Serial PCM/ADPCM transfer data rate from 128 to 2048 Kbps * Universal programmable dual tone generator such as DTMF application * Noise burst detection algorithm for ADPCM receive path * Analog input: differential OP amplifier with external gain adjustment for microphone interface * Programmable transmit gain, receive attenuation, and sidetone gain * Analog output:
- Differential power driver with 300 load and external gain adjustment - Differential auxiliary driver with 300 load for ringer interface
* 3 Volt regulator for digital circuit * 5 Volt charge pump for analog circuit low voltage applications * 16 Setup and status registers with 8 bits for monitoring microcontroller applications * Packaged in 28-pin DIP/SOP
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3. PIN CONFIGURATION
TG TITI+ VAG RO AXOAXO+ V DSP V EXT PI POPO+ PDI/RESET SSP En
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
V DD FSR BCLKR DR C1+ C1V SS MCLK DT BCLKT FST SSP Rx SSP Tx SSP CLK
Figure 3-1
4. PIN DESCRIPTIONS
4.1. Power Control Interface
PIN NAME VEXT VDSP PIN NO. 9 8 I/O I O FUNCTION This pin is the external power supply between 2.7 and 5.25 volt. This pin should be decoupled to VSS with a 0.1 F capacitor. This is the output of the on-chip 3 volt regulator which supplies the digital circuit of the chip. This pin should be decoupled to VSS with a 0.1 F ceramic capacitor. This pin cannot be used for powering external loads. This is the output of the on-chip 5 volt charge pump which supplies the analog circuit. When VEXT = +5V 5%, VDD is an input and should be connected to VEXT externally. Charge pump capacitor C1+ and C1- should not be used and BR0[b2] must be written into logic "1". In this case VEXT and VDD can share the same 0.1 F decoupling capacitor to VSS. When VEXT = 2.7 to 5.25 volt, VDD is a 5 volt charge pump output and should not be connected to VEXT. VDD should be decoupled to VSS with a 0.1 F capacitor. This pin cannot be used for powering external loads. This pin connects the analog and digital ground and is typically connected to 0 volt.
VDD
28
I/O
VSS
22
I
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4.1. Power Control Interface, continued
PIN NAME VAG
PIN NO. 4
I/O O
FUNCTION This is the analog ground output pin which supplies a 2.5 volt reference voltage for all analog signal processing. This pin should be decoupled to VSS with 0.1 F capacitor. This pin becomes high impedance when the chip enters an analog power down mode. The charge pump capacitor pins. When VEXT = +5V 5%, these capacitors C1+ and C1- should not be used and BR0[b2] must be written into logic "1". When VEXT = 2.7 to 5.25 volt, a 0.1 F capacitor should be placed between C1+ and C1-. The power down/reset input pin. When at logic 0, the chip enters a power down mode. When it switches from logic 0 to logic 1, this chip is active and resets the ADPCM transcoder and all circuits.
C1+, C1-
23, 24
I
PDI/RESE T
13
I
4.2. Analog Interface
PIN NAME TG PIN NO. 1 I/O O FUNCTION This pin is the analog output of the transmit input amplifier. It can be used to set the gain by external resistors. When the chip is in analog power down mode, this pin is high impedance. This pin is the inverting input of the transmit input amplifier. Connecting this pin and TI+ (pin-3) to VDD will force TG into a high impedance state. The non-inverting input of the transmit input amplifier. Connecting this pin and TI- (pin-2) to VDD will force TG to be high impedance. Note this pin may be connected to the VAG pin for an inverting configuration if the input signal is referenced to the VAG pin. This pin is the non-inverting analog output of the receive smoothing filter. This pin can typically drive a 2 K load to 1.13 volt peak referenced to the VAG pin. This pin may be dc referenced to either the VAG pin or VEXT/2 determined by BR2 (b7). When the chip is in analog power down mode, this pin is high impedance. This pin is the auxiliary inverting analog output. This pin can drive a 300 load differentially. This pin may be dc referenced to either the VAG pin or VEXT/2 by BR2 (b7). When the chip is in analog power down mode, this pin is high impedance. This pin is the auxiliary non-inverting analog output. This pin can drive a 300 load differentially. This pin may be dc referenced to either the VAG pin or VEXT/2 by BR2 (b7). When the chip is in analog power down mode, this pin is high impedance.
TI-
2
I
TI+
3
I
RO
5
O
AXO-
6
O
AXO+
7
O
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4.2. Analog Interface, continued
PIN NAME PI
PIN NO. 10
I/O I
FUNCTION This pin is the inverting input to the PO- (pin-11) power amplifier. It may be dc referenced to either the VAG pin or VEXT/2 by BR2 (b7). This pin and PO- are used to set the gain by using external resistors. Connecting this pin to VDD will power down the chip and the PO+ and PO- outputs will be high impedance. This pin is the inverting power amplifier output. Its operation is same as the AXO- (pin-6). In the application, this pin can drive the speaker on the receiver. This pin is the non-inverting power amplifier output. Its operation is the same as the AXO+ (pin-7). In the application, this pin can drive the speaker of the receiver.
PO-
11
O
PO+
12
O
4.3. ADPCM/PCM Serial Interface
PIN NAME MCLK PIN NO. 21 I/O I FUNCTION This pin is the system master clock input pin. It typically accepts 10.24 MHz or 16.384 MHz for Winbond cordless applications. This pin is the oscillator input. This pin is an 8 KHz pulse train for transmission of frame syncs. This pin synchronizes the output of the DT pin (pin-20). The bit clock for transmission. It shifts out the data on the DT pin on the rising edge. The frequency may vary from 128K to 2048 KHz. This pin is tri-state output data for transmission controlled by FST and BCLKT pin. This pin is an 8K Hz pulse train to receive frame syncs. This pin synchronizes the input of the DR pin (pin-25). This pin is the receive bit clock. It shifts data on the DR pin into the chip on the falling edge. The frequency varies from 128K to 2048 KHz. This pin is the receive input data controlled by the FSR and BCLKR pins.
FST BCLKT
18 19
I I
DT FSR BCLKR
20 27 26
O I I
DR
25
I
4.4 Serial Setup Port(SSP) Interface
PIN NAME SSP EN PIN NO. 14 I/O I FUNCTION This pin is the enable signal for SSP setup. This pin is held low to select the16 control and status registers. There are two timing controls. One is for double 8 bit transfer mode; the other control is for the single 16 bit transfer mode. See the timing diagram, Figure 7-6 to 7-9, in Section 7.4.
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4.4 Serial Setup Port(SSP) Interface, continued
PIN NAME SSP CLK
PIN NO. 15
I/O I
FUNCTION This pin is the clock for SSP setup. Note that data is shifted out of the SSP on the falling edge of this pin, and shifted into the SSP on the rising edge. The SSP CLK can be any frequency from 0 to 2048 KHz. This pin is the tri-state output data for SSP transmission controlled by the SSP CLK pin (pin-15). This pin is the receive input data for the SSP controlled by the SSP CLK pin (pin-15).
SSP TX SSP RX
16 17
O I
5. SYSTEM DIAGRAM
5.1 Pair Gain System
Applications for this device include the public switching telephone system. One such application is the pair gain system shown in Figure 5-1. The figure illustrates how the chip is used in a pair gain system to connect the telephone system between end users and the central office terminal. These chips are used on devices installed in both the central office terminal (COT) and in the remote office terminal (ROT). If the chip is operating in 32 Kbps ADPCM mode, the COT and ROT must use four chips for 4-channel communication because the U interface chip can support 2B channel, i.e., 128K bps. In the transmission path, the telephone system first sends the analog signal to the ADPCM chip in the ROT to compress it into a 32 Kbps digital signal. The U interface can then build a 2B+D channel, 128 Kbps, with four ADPCM chip channels, and send the 128 Kbps digital signal to the COT. After receiving the digital signal, the U interface in the COT separates the 128 Kbps data into four ADPCM channels (32 Kbps) and sends this data to the chip to execute the ADPCM decoder and for reconstruction into an analog signal. The analog signal is then sent to the central office (CO) to complete the transmission operation. For the receive path it is the reverse operation of the transmission path mentioned above. In a pair gain system, the analog signal (voice signal, or modem signal) is digitized and compressed to a ADPCM signal e.g. 32 Kbps ADPCM. The subscriber loop, the connection between the end user and the central office, is digitized by the U interface transceiver. This provides two B-channels (2 x 64 Kbps) for data and one D channel for signaling. In short, data can be transmitted and received on the subscriber loop via the U interface transceiver. One B-channel can carry 64 Kbps data, i.e. two 32 Kbps ADPCM channels. Therefore the pair gain system can supply four telephones.
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Remote Office Terminal (ROT)
Analog ADPCM Codec
Central Office Terminal (COT)
ADPCM Codec Analog
Centeral Office (CO)
Channel 1
Analog
ADPCM Codec
ADPCM Codec U interface 2B+D U interface 2B+D
Analog
Channel 2
Analog
ADPCM Codec
ADPCM Codec
Analog
Channel 3
Micro-Controller
Micro-Controller
Analog
ADPCM Codec ADPCM Codec Analog
Channel 4
End User Telephone System
Figure 5-1 System Diagram for Pair Gain Application
5.2. Cordless Phone System
Figure 5-2 shows a cordless phone system block diagram. On the transmission side, the voice is sent to the W9320 ADPCM Codec from the external microphone. First, the analog speech signal is digitized into a 14-bit linear signal and compressed into 32 Kbps ADPCM data. The compressed signal is then sent to the W9310F SST which provides all the baseband functions required for an FCC Part 15 compliant cordless phone. The SST W9310 will generate the spread spectrum binary sequence for output to an RF modulator. The microprocessor manages the other functions of the cordless phone such as the keypad and display control. On the receive side, the WHT9360 RF Module converts the received signal to baseband. The W9310 SST then performs the de-correlation and demoulation and sends the 32K bps speech signal into the W9320 ADPCM. The W9320 then reconstructs the digital speech signal into an analog signal using the 32K ADPCM decoder before sending this analog signal to the speaker.
Antenna Microphone
ADPCM Voice Codec W9320
Spread Spectrum Transceiver SST W9310F
RF Module WHT9360
Speaker
Microprocessor W921E880F
Figure 5-2 System Diagram for Cordless Phone Application
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6. BLOCK DIAGRAM
Codec-filter
DSP Engine
Digital Rx Gain ADPCM Decoder
PO+ POPI RO AXO+ AXOTITI+ TG
VAG
+ + + + Vref
-
DR FSR BCLKR
Analog Smoothing Filter
Analog LPF
Digital Demodulator
Digital Anti-Alias Intp. Filter
Rx Atten. Control
NoiseBurst Detection
Sidetone Gain
Universal Tone Generator
Serial Data Port (SDP)
+
Tx Gain Control
Analog Modulator
Digital Anti-aliasing Dec. Filter
FST BCLKT DT
Digital HPF
Mu/A Law Expander or Linear
ADPCM Encoder
2.5V Reference Voltage
Power Supply Management System
Mu/A Law Compressor
VEXT C1+ C1VDD VDSP
Charge-Pump & 5 volt Regulator for Analog Processing
3 volt Regulator for Digital Signal Processor
Serial Setup Port & 16 * 8 Bits Setup and Status Registers
Sequence and Control
MCLK
PDI/RESET
SSP EN
SSP CLK
SSP Tx
SSP Rx
Figure 6-1 Winbond ADPCM Codec Block Diagram
7. FUNCTIONAL DESCRIPTIONS
Figure 6-1 illustrates the functional blocks of the Winbond ADPCM codec. The chip can be divided into four subsystems which are described in the following subsections.
7.1. Power Supply Management System
In this block two groups comprise the power supply management system. One group is a 5-volt power supply system for all analog signal processing. The second group is a 3-volt power supply system for all digital signal processing. 7.1.1. Power Supply for All Analog Signals Processing All analog circuits except for output power amplifiers AXO and PO are supplied with 5-volt power. This voltage may be applied directly to the VDD pin or by the 5 volt charge pump circuit. Note that the power drivers AXO and PO are powered by the VEXT pin which is the main positive power supply pin. When VEXT = +5V 5% (e.g. base station applications) VDD is an input pin and should be connected externally to the VEXT pin. The charge pump capacitor C1+ and C1- should not be used and the BR0[b2] must be set as a logic "1" to disable the charge pump circuit. In this case VEXT and VDD can share the same 0.1 uF decoupling capacitor to VSS. When VEXT = 2.7 to 5.25 volts (e.g. battery applications) VDD is a 5 volt charge pump circuit output and should not be connected to VEXT. VDD should be decoupled to Vss with a 0.1 F capacitor. This pin cannot be used for powering external loads. -8-
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7.1.2. Power Supply for All Digital Signals Processing All digital circuits are supplied by the VDSP pin from a 3-volt regulator circuit. This reduces the chip power consumption. Whatever the value on the power supply pin VEXT, range from 2.7 to 5 volts, the digital circuits will always be powered by a 3 volt voltage supply. Note that the VDSP pin should be decoupled to Vss with a 0.1 F capacitor and that this pin cannot be used for powering external loads. 7.1.3. Reference Voltage Control System All analog reference voltages such as power amplifier RO, AXO, PO is 2.5 volt or VEXT/2 determined by BR2(b7).
7.2. Codec-Filter
This device has a built in linear 14-bit PCM codec-filter using technology. There are two paths in the block, a transmit path and a receive path. 7.2.1. Transmit Path in Codec-Filter An analog signal input, from a microphone interface, is passed to three terminal operational amplifiers (TI+, TI-, TG) driving a typical 2 K load externally to amplify the input analog signal. The analog signal can then be set to have further transmission gain from 0 to +7 dB, in 1 dB steps by the transmit gain control block. The gain is programmed through the SSP port in BR1(b2:b0). The modulator block oversamples the analog signal at 1.024 MHz with one bit resolution. The next antialiasing decimation filter reduces the sampling frequency from 1.024 MHz (1 bit) to 32 KHz (15 bit). Digital biquad filters perform the decimation from 32K to 8 KHz and CCITT low-pass filtering at 3400 Hz. The digital HPF block performs the high-pass filtering at 300 Hz. In the final step, the 14 bit A/D conversed data is sent by the transmit path to the DSP engine for further signal processing (e.g. by the ADPCM encoder). 7.2.2. Receive Path in Codec-Filter A 14-bit linear digital signal from the Rx Attenuation control block in the DSP engine is first passed to the digital anti-aliasing interpolation filter block. The interpolation block performs the reverse operation of the decimation filter (described above in the transmit path) and the sampling rate will be increased from 8 KHz (14 bits) to 1.024 MHz (14 bits). The digital demodulator will then reduce the 14-bit samples (1.024 MHz) to 1 bit (1.024 MHz). The digital output signal will be passed to a 3400 Hz switched capacitor low-pass filter with sin(x)/x correction and an analog smoothing filter to reduce the spectral components of the switched capacitor filter. Finally, the analog output signal is sent to the power amplifier, RO, which is capable of driving a 2 K load connected to to the VAG pin, and high current analog output driver AXO simultaneously with a 300 differential load. Note the device provides another power amplifier, PO, connected in a push-pull configuration. The AXO and PO have different circuit configurations for different applications. The AXO is for handset ringer applications, but the PO driver can accommodate large gain ranges by adjusting two external resistors for applications such as driving a telephone line or a handset receiver.
7.3. DSP Engine
This block is the kernel of the ADPCM transcoder and tone generator. There are two paths in this block, a transmit path and a receive path.
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7.3.1. Transmit Path in the DSP Engine A linear 14 bit sample input from the transmit path of the Codec-filter block is sent in three processing directions: sidetone gain process, Mu/A law compressor/Linear, and ADPCM encoder/ tone encoder. In the sidetone gain block, the input sample is fedback to the receive path and is summed with the output of the digital receive gain. The value is kept in the -70 dB to -8.5 dB range by the SSP port in BR1(b6:b4).The A/D output is then saved linearly into BR9(b7:b0) & BR10(b7:b2). The ADPCM encoder/tone encoder provides 16 Kbps, 24 Kbps, or 32 Kbps ADPCM, or 64 Kbps PCM respectively, as determined by the length of the transmit frame sync (pin 18). The length of the frame sync is calculated by the number of falling edges at the BCLKT pin when the transmit frame sync FST pin is high. Because the frame sync clock is 8 KHz, the encode interrupt is performed once every 125 S. As a default value the transmit ADPCM will be delayed by two frames after being requested, i.e. if the current frame request is for ADPCM operation, it will be computed in the next frame and the ADPCM result is transmitted in the next two frames. For applications such as the signaling channel of T1 frame structure the delay status can be configured to a total of 6 frames by the SSP port in BR7(b5). The ADPCM output result will be sent to the serial data port (SDP) on the DT pin and the output data rate from 128 KHz to 2048 KHz will be controlled by the serial data port on the BCLKT pin. In the universal tone generator mode, the input of the ADPCM encoder comes from the output of the universal tone generator, not from the transmit path in the codec-filter. The ADPCM encoder outputs the tone ADPCM signal through pin DT. 7.3.2. Receive Path in DSP Engine The device receives data from the DR pin via the serial data port (SDP) under the control of the BCLKR and FSR pins. The clock of the receive frame sync FSR is 8 KHz. The ADPCM decoder receives one decode interrupt every 125 S. The serial data rate in the BCLKR is in the 128 KHz to 2048 KHz range. The input parameter data is sent to the ADPCM decoder which also provides 16 Kbps, 24 Kbps, or 32 Kbps ADPCM or 64 Kbps PCM, is determined by the length of the receive frame sync FSR pin. The length of the frame sync is calculated by the number of falling edges at the BCLKR pin when the receive frame sync FSR pin is high. The ADPCM decoder consists of a sync adjustment operation for the correction of sync. tandem application, except when the receive digital gain is used for a handset application. The digital receive gain is programmed from -12 dB to +12 dB through the SSP port in BR3(b6:b0). In order to prevent noise from influencing the result of the ADPCM decoder, the noise burst detection algorithm can be enabled by setting the BR7(b6) register to detect interfering sounds and to mute the receive path. The reconstructed linear PCM will be compressed by the Mu/A law compressor block and sent to BR11 (b7:b0) on the SSP port after sync. adjustment in G.726 for CCITT test mode. After the control of digital receive gain, the synthesized PCM data will be added to the feedback signal of the transmit path in the sidetone gain block. The sum value is then passed to the Rx attenuation control block to protect the output driver, RO, from distortion when the amplitude of the synthesis data is too large (e.g. battery applications). The gain of the Rx. attenuation block is programmed through the BR2 (b2:b0) register in the SSP port. A receive attenuation range of from 0 to -7 dB can be programmed in 1 dB steps. If the device enables the universal tone generator, the function of the ADPCM decoder will be disabled. Different tone types (i.e. tone 1 and tone 2) can be programmed through the BR7, BR4, and BR5 registers in the SSP port. The tone generator can be used to generate DTMF tones, different ringing tones, and call progress tones for handset applications. In telephone line applications, this tone generator can be used for signaling on the line. - 10 -
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7.3.3. Frame Sync. Types The frame sync operation uses two industrial control types for the transfer of the ADPCM or PCM data words. These two types are the long frame sync and short frame sync. 7.3.3.1. Long Frame Sync The long frame sync types for various data rates are shown in Figure 7-1 to 7-4. The bit rate for the ADPCM or PCM encoder and decoder is determined by the length of the frame sync pin (FST or FSR). The length of the frame sync is calculated by the number of falling edges at the BCLKT or BCLKR pin when the frame sync FST or FSR pin is high. For example, if the number of the falling edges on the BCLKT or BCLKR pin is equal to 2 when the frame sync is high, this corresponds to the 16 Kbps bit rate for the encoder and decoder of the ADPCM operation. If the number is 8, the device becomes 64 Kbps PCM operator. The device shifts out the data on the DT pin at the BCLKT rising edge and shifts in the data on the DR pin at the BCLKR falling edge. The length of the frame sync may be changed on a frame by frame basis. 7.3.3.2. Short Frame Sync The short frame sync types for 32 Kbps ADPCM timing is shown in Figure 7-5. The bit rate for this type of frame performs only 32 Kbps ADPCM encoding and decoding. The length of the frame sync is equal to 1. The device shifts out data on the DT pin at the BCLKT rising edge and shifts in data on the DR pin at the BCLKR falling edge. Switching between long frame sync and short frame sync without going through a power down operation is not recommended.
FST (FSR) BCLKT (BCLKR) DT DR
Don't Care 1 2 3 4 5 6 7 8
MSB
D1 D0
LSB LSB
D0 Don't Care
MSB
D1
Figure 7-1 Long Frame Sync for 16 Kbps ADPCM Timing
FST (FSR) BCLKT (BCLKR) DT
Don't Care 1 2 3 4 5 6 7 8
MSB
D2 D1 D0
LSB
MSB
LSB
D1 D0 Don't Care
DR
D2
Figure 7-2 Long Frame Sync for 24 Kbps ADPCM Timing
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FST (FSR) BCLKT (BCLKR) DT DR
1 2 3 4 5 6 7 8
MSB
D3 D2 D1 D0
LSB
MSB
Don't Care
LSB
D2 D1 D0 Don't Care
D3
Figure 7-3 Long Frame Sync for 32 Kbps ADPCM Timing
FST (FSR) BCLKT (BCLKR) DT DR
Don't Care 1 2 3 4 5 6 7 8
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
MSB
D7 D6 D5 D4 D3 D2 D1 D0
LSB
Don't Care
Figure 7-4 Long Frame Sync for 64 Kbps ADPCM Timing
FST (FSR) BCLKT
1 2 3 4 LSB D2 D1 D0 LSB D2 D1 D0 Don't Care 5 6 7 8
(BCLKR)
MSB
DT DR
D3 MSB Don't Care D3
Figure 7-5 Short Frame Sync for 32 Kbps ADPCM Timing
7.4. Serial Setup Port (SSP)
The W9320 has sixteen 8-bit wide setup and status monitoring functions via the serial setup port (SSP). microcontroller such as the Winbond W921E880. The (marked as SSP Tx, SSP Rx, SSP CLK, and SSP EN) - 12 registers, BR0--BR15, for controlling and The SSP may be used by an external SSP has a full-duplex four wire interface for communicating with an external micro-
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controller. Two timing controls, a double 8-bit transfer mode and a single 16-bit transfer mode, are available when SSP EN is held low to select the setup registers. The data rate for the SSP CLK ranges from 0 to 2048 KHz. The data is shifted out of the SSP port on the falling edge of SSP CLK, and shifted into the SSP port on the rising edge of the SSP CLK. This latch operation is the reverse of the serial data port in the DSP engine. The 16 byte registers are selected by bits 3 to 0 in the first byte from the SSP Rx pin as shown in Figure 7-6 to 7-9. Bit 7 of the first byte indicates whether the status is read (logic 1) or write (logic 0). The second byte is the data word (D7:D0). The description of setup and status registers, BR0--BR15 is described in greater detail in the next section 8. (Control and Status Registers).
SSP EN
SSP CLK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SSP Tx
High Impedence
SSP Rx
W
Don't Care A3
A2
A1
A0
Don't Care
D7
D6
D5
D4
D3
D2
D1
D0
Don't Care
Figure 7-6 Double 8 bit for Write Operation of SSP Register
SSP EN
SSP CLK
1
2
3
4
5
6
7
8
1
2
3
4
5
6
7
8
SSP Tx
D7
D6
D5
D4
D3
D2
D1
D0
SSP Rx
R
Don't Care A3
A2
A1
A0
Don't Care
Figure 7-7 Double 8 bit for Read Operation of SSP Register
SSP EN
SSP CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
High Impedence SSP Tx
SSP Rx
W
Don't Care A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Don't Care
Figure 7-8 Single 16 bit for Write Operation of SSP Register
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SSP EN
SSP CLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
SSP Tx
D7
D6
D5
D4
D3
D2
D1
D0
SSP Rx
R
Don't Care
A3
A2
A1
A0
Don't Care
Figure 7-9 Single 16 bit for Read Operation of SSP Register
7.5. Sequence and Control
This block generates some internal clocks, providing clocks such as 1.024 MHz and 8 KHz for codec-filter operation. The master clock MCLK, which supports the clock of the DSP engine, may be asynchronous to all other blocks. Its frequency is typically 10.24 MHz or 16.384 MHz for cordless applications using Winbond chips. The codec-filter may use the BCLKR pin as a direct 1.024MHz input. The rising edge of this input clock must be approximately aligned with the rising edge of the FST. This mode requires that the ADPCM transmit and receive be controlled by the BCLKT pin. This is configured by the SSP port through the BR0(b7) register. There are two ways of forcing the device into a low power consumption condition in power down mode. One way is the hardware power down mode where the PDI/RESET pin is held to logic 0. The other way is the software power down mode where the register BR0(b1:b0) is set through the SSP. When the BR0(b1) setting initiates an analog power down, all clocks for analog signal processing will be halted. To initiate a digital power down, the BR0(b0) register can be programmed to logic 1 to halt all clocks for all digital signal processing. When the chip is powered down, the VAG, TG, RO, PO, AXO, DT and SSP Tx outputs are all high impedance. When the power is reactivated from the power down mode, the ADPCM algorithm is reset to the CCITT initiate state.
7.6. I/O Level
Digital I/O for the device can be programmed in either Mu-law or A-law. Full scale and zero words for these two log-PCM forms are shown in Table 7-1. For analog signal processing, the maximum transmit level is 3.17 dBm0 for Mu-Law or 3.14 dBm0 for A-Law. These values meet the CCITT G.711specifications. MU-LAW Level + max. scale +Zero - Zero - max. scale Sign 1 1 0 0 Segment Bits 000 111 111 000 Step Bits 0000 1111 1111 0000 Sign 1 1 0 0 A-LAW Segment Bits 010 101 101 010 Step Bits 1010 0101 0101 1010
Table 7-1 Full Scale and Zero Word for Mu/A-Law
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8. CONTROL AND STATUS REGISTERS
8.1. Introduction
There are 16 available byte setup and status registers for the SSP port. The functional description and read/write status of each bit are illustrated in the sections that follow. The read or write status described in Table 8-1 is indicated by the symbol r, w, ro. SYMBOL r/w ro ro/wo TYPE Read/Write MEANING Data may be read from the SSP port or written into the SSP port by micro-processor Read Only Data may only be read from the SSP port. Writing to this port has no effect. Read Only/Write Only Data may be read or written by an external micro-processor and internal chip simultaneously. The value is written into the bit and read back by the external micro-controller
Table 8-1 Read/Write Status Description in SSP Byte Register
8.2. Byte Register Description
There are 16 byte registers for controlling and monitoring the status of the chip. These registers are labeled BR0 to BR15. The descriptions are as follows. Note that "setting" is corresponding to logic "1" and "clearing" is corresponding to logic "0".". 8.2.1. Byte Register 0 (BR0) This is a control register. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 BR0 B6 B5 B4 B3 Function Mode Select[0] r/w B2 Charge Pump Disable r/w B1 Analog Power Down r/w B0 Digital Power Down r/w
Function Ext 1024 Mu/A Law Analog Mode Select Loopback KHz Select[1] Clock r/w r/w r/w r/w
External 1024 KHz Clock (b7): This bit controls a mux. When this bit is cleared, the mux selects the 1024 KHz clock from the internal clock generator. When this bit is set, the BCLKR pin is used to provide an external 1024 KHz clock and the internal BCLKR is connected to BCLKT; the BR0[b1] must be set to "1" for reset codec. Mu/A Law (b6): When this bit is set to logic zero, the device selects Mu-Law companding of the Log-PCM. Setting this bit selects the A-Law companding of the Log-PCM. Analog Loopback (b5): Setting this bit causes an analog loopback from the receive path to the transmit path. Internally the RO output in the receive path is routed to the transmit gain control in the transmit path; the op-amp TG is bypassed.
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Mode Select[1:0] (b4:b3): The function modes are shown in Table 8-2. The ADPCM Codec mode performs a combination of PCM codec and ADPCM transcoder in full duplex. The PCM codec mode is a subset of the ADPCM codec mode, where only the PCM codec is executed. The CCITT test mode uses the CCITT ADPCM test vectors to do conformance testing. Enabling this mode will remove the codec-filter operation. The test vectors go through the SSP port in BR9[b7:b0] and BR10[b7:b0]. See the BR9 and BR10 descriptions for more details. The battery test mode allows testing of the voltage present at the VEXT pin. In this mode, the HPF output in register BR8[b4] must be disabled. Note that the steady linear code for the VEXT pin will be delayed by about 60 samples. The output result of linear 14 bits is stored in registers BR9 and BR10. FUNCTION MODE SELECT[1:0] (B4:B3) 00 01 10 11 TYPE ADPCM Codec PCM Codec CCITT Test Battery Test
Table 8-2 Function Mode Selection
Charge Pump Disable (b2): Setting this bit disables the 5 volt charge pump. In this mode, the charge pump capacitor C1+ and C1- should not be used and the VDD pin should be connected externally to the VEXT pin. Analog Power Down (b1): Setting this bit causes an analog power down. In this mode, all clocks for analog processing (e.g. the codec) will be halted to reduce power consumption. The analog circuit will not operate normally until this bit is cleared. Digital Power Down (b0): Setting this bit causes a digital power down. In this mode, all clocks for digital processing (e.g. the DSP engine) will be halted to reduce power consumption. The digital circuit and the ADPCM initialization will not operate until this bit is cleared. 8.2.2. Byte Register 1 (BR1) This register controls the sidetone gain value and transmit gain. This register can also mute the transmit signal. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 Reserved BR1 B6 Sidetone Gain[2] r/w B5 Sidetone Gain[1] r/w B4 Sidetone Gain[0] r/w B3 Transmit Mute r/w B2 Transmit Gain[2] r/w B1 Transmit Gain[1] r/w B0 Transmit Gain[0] r/w
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Reserved (b7): This bit is reserved. Sidetone[2:0] (b6:b4): These two bits control the sidetone attenuation. The sidetone attenuation can range from -U to -8.5 dB as shown in Table 8-3. Transmit Mute (b3): Setting this bit will mute the transmit path in the codec-filter block. A send zero is sent to the DSP engine for further processing. Transmit Gain (b2:b0): These three bits control the transmit gain control as shown in Table 8-4. The gain range can be set in the 0 to 6.8 dB range in +1 dB steps. SIDETONE[2] (B6) 0 0 0 0 1 1 1 1 SIDETONE[1] (B5) 0 0 1 1 0 0 1 1 SIDETONE[0] (B4) 0 1 0 1 0 1 0 1
Table 8-3 Sidetone Attenuation
SIDETONE ATTEN. (DB) -U -21.5 -18.0 -15.0 -13.5 -11.5 -10.5 -8.0
TRANSMIT GAIN[2] (B2) 0 0 0 0 1 1 1 1
TRANSMIT GAIN[1] TRANSMIT GAIN[0] (B1) (B0) 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1
Table 8-4 Transmit Gain Control
TRANSMIT GAIN CONTROL(DB) 0 +1.5 +2 +3 +4 +5 +6 +6.8
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8.2.3. Byte Register 2 (BR2) This register controls the operations of the receive path in the code-filter block. All bits are cleared when the PDI/RESET pin is set to logic zero. B7 Reference BR2 Point Select r/w r/w r/w r/w r/w r/w r/w B6 AXO Enable B5 PO Disable Reserved B4 B3 RO Mute B2 Receive Atten.[2] B1 Receive Atten.[1] B0 Receive Atten.[0]
Reference Point Select (b7): This bit determines the reference voltage for power amplifiers such as RO, AXO, and PO. The output of the VAG pin is the reference voltage. Setting this bit sets the reference voltage to 2.5 volts. When this bit is cleared, the reference voltage is the default value of VEXT/2. AXO Enable (b6): This bit determines the status of the power amplifier AXO. Setting the bit will enable the operation of the AXO amplifier. When this bit is cleared, the amplifier AXO will be disabled by default. In power down mode, the output pins of AXO are high impedance. PO Disable (b5): This bit determines the status of power amplifier PO. Setting the bit will disable the operation of PO amplifier. When this bit is cleared, the amplifier PO is enabled by default. In the power down mode, the output pins of PO are high impedance. Reserved (b4): This bit is reserved. RO Mute (b3): Setting this bit will force the input of the RO amplifier to ground. The RO remains offset in order to avoid audible " pops" when turning the block on and off. Receive Attenuation[2:0] (b2:b0): These three bits control the receive attenuation as shown in Table 8-5. The attenuation range can be set from 0 to -7 dB in -1 dB steps. RECEIVE ATTEN.[2] (B2) 0 0 0 0 RECEIVE ATTEN.[1] B1) 0 0 1 1 RECEIVE ATTEN.[0] (B0) 0 1 0 1 RECEIVE ATTENUATION (DB)
0
-1 -2 -3
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Continued
RECEIVE ATTEN.[2] (B2) RECEIVE ATTEN.[1] B1) 1 1 1 1 0 0 1 1
RECEIVE ATTEN.[0] (B0) 0 1 0 1
RECEIVE ATTENUATION (DB) -4 -5 -6 -7
Table 8-5 Receive Attenuation Control
8.2.4. Byte Register 3 (BR3)
B7 BR3 Digital Rx Gain Enable r/w r/w r/w r/w r/w r/w r/w r/w B6 Dig. Rx Gain[6] B5 Dig. Rx Gain[5] B4 Dig. Rx Gain[4] B3 Dig. Rx Gain[3] B2 Dig. Rx Gain[2] B1 Dig. Rx Gain[1] B0 Dig. Rx Gain[0]
This register contains information on the digital receive gain. All bits are cleared when the PDI/RESET pin is set to logic zero. Digital Rx Gain Enable (b7): Setting this bit will enable the digital receive gain routine in the DSP engine. The receive gain can be programmed by setting the gain factors defined in this register BR3[B6:B0]. When this bit is cleared, the digital receive gain routine is disabled. Digital Rx Gain[6:0](b6:b0): These seven bits show the value of the digital receive gain factor. The gain value is calculated as follows: 2 * b6 + b5+ 1/2 *b4 + 1/4 * b3 + 1/8 *b2 +1/16 *b1 +1/32 * b0 The first two bits (b6:b5) are integers and the last four bits are fractions. The decimal point is placed after bit 5. The gain range is from -12 dB to +12 dB. 8.2.5. Byte Register 4 (BR4)
B7 TonePar[7] BR4 r/w r/w r/w r/w r/w r/w r/w r/w B6 TonePar[6] B5 TonePar[5] B4 TonePar[4] B3 TonePar[3] B2 TonePar[2] B1 TonePar[1] B0 TonePar[0]
This register holds the parameters for the tone generator. All bits are cleared when the PDI/RESET pin is set to logic zero. Tone Generator Parameters[7:0](b7:b0): These seven bits contain the eight LSB frequencies or tone generator attenuation coefficients. The tone generator is enabled when the BR7[b3] register is set to 1. The four MSB tone parameters are placed in BR5[b3:b0]. Switching between the frequency and attenuation factor is determined by the BR5[b7:b6] register. Publication Release Date: August 1997 Revision A1
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8.2.6. Byte Register 5 (BR5) This register holds the parameters for noise burst detection and the tone generator. The noise burst detection and tone generator modes are enabled through the BR7(b3) register. All bits are cleared when the PDI/RESET pin is set to logic zero.
B7 BR5 NB Thd[7]/ ToneAddr[1] r/w B6 NB Thd[6]/ ToneAddr[0] r/w B5 NB Thd[5]/ Don Care r/w B4 NB Thd[4]/ Don Care r/w B3 NB Thd[3]/ TonePar[11] r/w B2 NB Thd[2]/ TonePar[10] r/w B1 NB Thd[1]/ TonePar[9] r/w B0 NBThd[0]/ TonePar[8] r/w
Noise Burst Detect Threshold[7:0] (b7:b0): When the device is in the noise burst detection mode (i.e. BR7[b3] = 0 and BR7[b6] = 1) these eight bits contain the threshold for noise burst detection. The detected algorithm use the frequency value to decide whether the noise is present or not. We suggest a threshold value greater than 80 (to be written in decimal format, i.e. 4 KHz above). Tone Generator Address[1:0](b7:b6): When the tone generator is enabled, (i.e. BR7[b3] = 1), these two bits can be programmed to select the frequency or attenuation factor as shown in Table 8-6. Tone Generator Parameters[11:8](b3:b0): These four bits contain the four LSB frequencies or tone generator attenuation coefficients. The tone generator is enabled when the BR7 (b3) register is set to 1. The last eight LSBs are placed in the BR4[b7:b0] register. Switching between the frequency and attenuation factor is determined by bit 7 and bit 6.
TONE ADDRESS[1] (B7) 0 0 1 1 TONE ADDRESS[0] (B6) 0 1 0 1 TONE PARAMETER SELECTION Frequency of Tone 1 Attenuation of Tone 1 Frequency of Tone 2 Attenuation of Tone 2
Table 8-6 Tone generator Address Parameters
8.2.7 Byte Register 6 (BR6)
B7 BR6 Reserved B6 Reserved B5 Reserved B4 Reserved B3 Reserved B2 Reserved B1 Reserved B0 Reserved
This register is reserved. The user should not read or write to this register. 8.2.8. Byte Register 7 (BR7) This register is used to enable noise burst detection and the tone generator. Additional options include 2/6 frame delay and writing ready status for the BR4 and BR5 registers. All bits are cleared when the PDI/RESET pin is set to logic zero.
B7 BR7 Ready for BR4 & BR5 ro B6 NB Detect Enable ro/wo B5 2/6 Delay r/w B4 Don`t Care B3 Tone Gen. Enable r/w B2 Reserved B1 Tone1 Enable r/w B0 Tone 2 Enable r/w
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Ready for Writing BR4 and BR5 (b7): This read-only bit indicates whether parameters have been written into the BR4 and BR5 register. This bit is set after writing to BR5. This bit is cleared when the internal DSP Engine reads from the BR4 and BR5 registers. Noise Burst Detect Enable (b6): This is a read-only/write-only bit. Setting this bit and bit 3 to 0 enables the noise burst detection routine. If noise is detected, this bit is cleared and can be polled by an external micro-controller. This mutes the receive path. 2/6 Delay (b5): This bit controls the frame delay status. Setting this bit inserts a 6-frame delay between frame control changes. Clearing this bit inserts a 2-frame delay between frame control changes. Don't Care (b4): No effect whenever the bit is read or written to by an external micro-controller. Tone Generator Enable (b3): Setting this bit performs the tone generator routine instead of the ADPCM decoder. In addition, the noise burst detection will be disabled. The result of the tone generator will be passed to the ADPCM encoder to compress the tone and transmit the encoded result to the DT pin. Reserved (b2):
This bit is reserved.
Tone 1 Enable (b1): Setting this bit enables the tone 1 routine for the tone generator. When this bit is cleared, the tone1 routine is disabled. Tone 2 Enable (b0): Setting this bit enables the tone 2 routine for the tone generator. When this bit is cleared, the tone 2 routine is disabled. If DTMF is enabled, the user must set tone 1 and tone 2 to enable. 8.2.9. Byte Register 8 (BR8) This register contains miscellaneous control bits. All bits are cleared when the PDI/RESET pin is set to logic zero.
B7 S/W BR8 Encoder Reset r/w B6 S/W Decoder Reset r/w B5 Linear Codec Mode r/w B4 HPF Disable Reserved Reserved Reserved Reserved B3 B2 B1 B0
r/w
Software Encoder Reset (b7): Setting this bit forces the device to execute the ADPCM encoder initialization every time the encoder receives an interrupt. Publication Release Date: August 1997 Revision A1
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Software Decoder Reset (b6): Setting this bit forces the device to execute the ADPCM decoder initialization every time the decoder receives an interrupt. Linear Codec Mode (b5): Setting this bit forces the device to perform as an 8 bit linear codec. The 6 LSB linear A/D converted output from the codec-filter will be truncated in this mode. HPF Disable (b4): Setting this bit will disable the high pass filter (HPF) in the transmit path for applications such as battery test mode in BR0[b4:b3] = "1"". Reserved (b3:b0): These bits are reserved and should not be used by the user. CAUTION: Reserved bits (b3:b0) must be set to zero at all times for normal operation. 8.2.10. Byte Register 9 (BR9)
B7 Tx Log PCM[7]/ BR9 Linear PCM[13] ro/wo B6 Tx Log PCM[6]/ Linear PCM[12] ro/wo B5 Tx Log PCM[5]/ Linear PCM[11] ro/wo B4 Tx Log PCM[4]/ Linear PCM[10] ro/wo B3 Tx Log PCM[3]/ Linear PCM[9] ro/wo B2 Tx Log PCM[2]/ Linear PCM[8] ro/wo B1 Tx Log PCM[1]/ Linear PCM[7] ro/wo B0 Tx Log PCM[0]/ Linear PCM[6] ro/wo
This register contains the PCM value of the transmit path. If the PCM value comes from the transmit path of the codec-filter, then BR9 may be internally written into the most siginificant bits of the 14 bit linear PCM (b13:b6). If the device is for applications such as CCITT test mode i.e. BR0[b4:b3] = "0" then BR9 may read the companding Log-PCM from an external micro-controller to be used for the ADPCM encoder. In the 14 bit linear mode, the 8 MSB are stored into this register and the left 6 LSB will be placed in BR10[b7:b2]. See the description of BR10 for more details. Note that this register is read-only/write-only. 8.2.11. Byte Register 10 (BR10)
B7 Encoder Linear PCM[5] ro B6 Encoder Linear PCM[4] ro B5 Encoder Linear PCM[3] ro B4 Encoder Linear PCM[2] ro B3 Encoder Linear PCM[1] ro B2 Encoder Linear PCM[0] ro B1 Reserved B0 Reserved
BR10
This register contains the 6 LSB of the linear PCM value for the transmit path. The PCM value must come from the transmit path of the codec-filter and not from an external micro-controller. The left 8 MSB are stored into BR9[b7:b0]. See the description of BR9 for more details. Note that this register is read-only.
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8.2.12. Byte Register 11 (BR11)
B7 Rx LogBR11 PCM[7]/ DAC PCM[13] ro B6 Rx LogPCM[6]/ DAC PCM[12] ro B5 Rx LogPCM[5]/ DAC PCM[11] ro B4 Rx LogPCM[4]/ DAC PCM[10] ro B3 Rx LogPCM[3]/ DAC PCM[9] ro B2 Rx LogPCM[2]/ DAC PCM[8] ro B1 Rx LogPCM[1]/ DAC PCM[7] ro B0 Rx LogPCM[0]/ DAC PCM[6] ro
This register contains the PCM value of the receive path. The PCM value comes from the companding Log-PCM generated by the sync adjustment block of the decoder in CCITT test mode, i.e. BR0 (b4:b3) is set to logic "0". Note that, this register is read-only. The combined BR11 (b7:b0) and BR12 (b7:b2) value is the same as sending the D/A converter . 8.2.13. Byte Register 12 (BR12)
B7 DAC BR12 PCM[5] ro B6 DAC PCM[4] ro B5 DAC PCM[3] ro B4 DAC PCM[2] ro B3 DAC PCM[1] ro B2 DAC PCM[0] ro B1 Reserved B0 Reserved
This register contains the 6 LSB of the linear PCM value for the D/A converter. The PCM value cannot be entered by an external microcontroller. The left 8 MSB are stored into BR11[b7:b0]. See the description of BR11 for more details. Note that this register is read-only. 8.2.14. Byte Register 13 (BR13)
B7 BR13 Reserved B6 Reserved B5 Reserved B4 Reserved B3 Reserved B2 Reserved B1 Reserved B0 Reserved
This register is reserved and should not be used by the user. 8.2.15. Byte Register 14 (BR14)
B7 BR14 Reserved B6 Reserved B5 Reserved B4 Reserved B3 Reserved B2 Reserved B1 Reserved B0 Reserved
This register is reserved and should not be used by the user. 8.2.16. Byte Register 15 (BR15) This register shows the version number of this device.
B7 Reserved BR15 ro ro ro ro B6 Reserved B5 Reserved B4 Reserved B3 Vers.[3] B2 Vers.[2] B1 Vers.[1] B0 Vers.[0]
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Version[3:0] (b3:b0): These four bits determine the manufacturing version number of this chip.
9. ELECTRICAL CHARACTERISTICS
9.1. Absolute Maximum Ratings
(Voltage Referenced to VSS pin)
PARAMETER Power Supply Voltage Analog Input/Output Voltage Digital Input/Output Voltage Operating Temperature Storage Temperature
SYMBOL VEXT, VDD ----TOP TSTG
RATING -0.3 to 6 -0.3 to VDD + 0.3 -0.3 to VEXT + 0.3 -25 to +85 -85 to +85
UNIT V V V J J
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
9.2. DC Characteristics
(VSS = 0 volt TOP = -25 to +85 C)
PARAMETER Operating Voltage Operating Current
SYM. VEXT IEXT -----
CONDITION MCLK = 16.384 MHz, Charge Pump "N" no load MCLK Off All digital input pins All digital input pins DT, SSP Tx DT, SSP Tx VSS VIN VEXT VSS VIN VEXT All digital input pins to VSS
MIN. 2.7 ---
TYP. 3.0 ---
MAX. 5.25 25
UNIT V mA
Power Down Current Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High Current Input Low Current Input Capacitance
IPWDN VIH VIL VOH VOL IIL IIH CIN
--VEXT -0.5 0 VEXT -0.5 0 -10 -10 ---
-------------------
0.5 ----0.5 ----0.4 +10 +10 10
mA V V V V uA uA pF
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9.3. Analog Transmission Characteristics
(VDD = +5V 5%, VSS = 0 volt , Top = -25 to +85 C ; all analog signal referenced to VAG; 64 Kbps PCM; FST = FSR = 8 KHz; BCLKT = BCLKR = 2.048 MHz; MCLK = 16.384 MHz ; Unless otherwise noted)
9.3.1. Amplitude Response for Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Absolute Level Max. Transmit Level Frequency Response, Relative to 0 dbm0 @ 1020Hz LABS TXMAX GRTV 0 dBm0 = -3 dBm @ 600 -----15 Hz 50 Hz 60 Hz 200 Hz 300 to 3000 Hz 3300 Hz 3400 Hz 4000 Hz 4600 to 100, 000 Hz Gain Variation vs. Level Tone (1020 Hz relative to -10 dBm0) GLT +3 to -40 dBm0 -40 to -50 dBm0 -50 to -55 dBm0 0.549 1.130 --------------------------------------1.0 -0.20 -0.35 -0.8 -----0.3 -1.0 -1.6 MAX. -----40 -30 -26 -04 +0.15 +0.15 0 -14 -32 +0.3 +1.0 +1.6 RECEIVE MIN. -----0.5 -0.5 -0.5 -0.5 -0.20 -0.35 -0.8 -----0.2 -0.4 -0.8 MAX. ----0 0 0 0 +0.15 +0.15 0 -14 -30 +0.2 +0.4 +0.8 dB Vrms Vpk dB UNIT
9.3.2. Distortion Characteristics for Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Absolute Group Delay
(2) (1)
RECEIVE MIN. ----------------34 36 30 25 MAX. -------------------------
UNIT
MAX. 440 210 130 70 35 70 95 145 ---------
DABS DRTV
1600 Hz 500 to 600 Hz 600 to 800 Hz 800 to 1000 Hz 1000 to 1600 Hz 1600 to 2600 Hz 2600 to 2800 Hz 2800 to 3000 Hz
-------------------------
----------------36 36 29 25
S
Group Delay Referenced to 1600 Hz
Total Distortion vs. Level Tone (1020 Hz, Mu-Law, CMessage)
DLT
+3 dBm0 0 to -30 dBm0 -40 dBm0 -45 dBm0
dBC
Note: (1), (2): Guaranted by engineering test, not mass production.
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9.3.3. Noise Characteristic for Analog Transmission Performance
PARAMETER SYM. CONDITION TYP. TRANSMIT MIN. Idle Channel with Equipment Noise Spurious Out-of-Band at SPKO (300 to 3400 Hz @ 0 dBm0) In-Band Spurious (1020 Hz @ 0 dBm0) Crosstalk (1020 Hz @ 0 dBm0) NCTK 300 to 3000 Hz -----70 ---70 dB NIBS NIDE NSPO Mu-Law, C-Message 4600 to 7600 Hz 7600 to 8400 Hz 8400 to 100,000 Hz 300 to 3000 Hz --------------------MAX. 19 -------48 RECEIVE MIN. ----------MAX. +11 -30 -40 -30 -48 dB dBrn dB UNIT
9.4. Analog Electrical Characteristics
(OP Amplifer TG, RO; Power Amplifer AXO, PO; VDD = +5V 5%, Vss = 0V; Top = -25 to +85 C)
PARAMETER Input Offset voltage of TG Input Common Mode Voltage Load Capacitance for RO Load Resistance to VAG for TG, RO VAG Output Voltage Power Supply Rejection Ratio (0 to 100 KHz @ 100m Vrms to VDD with C-Message) Load Capacitance for AXO, PO
SYM. VOFIN VCMV CLRO RLD VAG PSRRdd
CONDITIONS TI+, TITI+, TIRO TG, RO to VSS TG
MIN. --1.0 --2 2.4 ---
TYP. --------2.5 40
MAX. 25 VDD -2.0 100 --2.6 ---
UNIT mV V pF K V dBC
CLAP
AXO- to AXO+; PO- to PO+
---
----
300
pF mV
Load Resistance differentially for AXO, PO Input Offset Voltage for PI
RLDAP
AXO- to AXO+; PO- to PO+
300
---
---25
VOFPI
ref to VAG
---
----
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9.5. Digital Switching Characteristics
9.5.1. Characteristic of Serial Data Port for Long Frame and Short Frame
(VEXT = +2.7 to 5.25V ; Vss = 0V; all digital circuits referenced to VSS; Top = -25 to +85 C, CL = 150 pF )
PARAMETER Master Clock Frequency Bit Clock Frequency Frame Sync. Frequency Clock Duty Cycle Rise Time Fall Time Frame Sync. Pulse Width Transmit Sync. Timing Receive Sync. Timing Setup Time for DR Valid Hold Time for DR Valid Output Delay Time for DT Valid Output Delay Time for DT High Impedance
SYM. TMAST TBCLK TSYNC DC TIR TIF TFSP TXS TSX TRS TSR TSTDR THDDR TDV TDHI
CONDITIONS MCLK BCLKT,BCLKR FST, FSR MCLK, BCLKT, BCLKR All digital input pins All digital input pins FST, FSR BCLKT to FST FST to BCLKT BCLKR to FSR FSR to BCLKR ----BCLKT to DT BCLKT to DT
MIN. 10.232 16.376 128 --45 ----100 20 80 20 80 20 50 10 10
TYP. 10.240 16.384 --8 50 -----------------------
MAX. 10.247 16.391 2048 -55 50 50 --------------140 140
UNIT MHz KHz KHz % nS nS nS nS nS nS nS nS nS
Note: these parameters are shown in Figure 9-1 and 9-2.
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tmast
tir
tif
MCLK
tfsp txs tsync
FST
tsx
BCLKT DT
1 MSB D1 tdv
2 D0
3 tdhi LSB
4
5
6
7
8
tfsp trs
tsync
FSR
tsr
BCLKR DR
1 MSB D1
2 tstdr D0
3 thddr LSB
4
5
6
7
8
Figure 9-1 Long Frame Sync, Timing
tfsp txs
tsync
FST BCLKT
tsx 3 tdhi D2 D1 D0
1 tdv MSB D3
2
4
5 LSB
6
7
8
DT
tfsp trs
tsync
FSR BCLKR
tsr 8
1 MSB
2 tstdr D2
3 thddr D1
4
5 LSB
6
7
DR
D3
D0
Figure 9-2 Short Frame Sync, Timing
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9.5.2. Characteristic of Serial Setup Port (SSP)
tcditdic tenc
SSP EN
tdhc tcen tsspc 1 trvb trva 2 3 4 tdvc b6 5 6 7 8
SSP CLK
SSP Tx SSP Rx
b7
b5
b4
b3
b2
b1
b0
R/Wb7
b6
b5
b4
b3
b2
b1
b0
Figure 9-3 Serial Setup Port (SSP) Timing
(VEXT = +2.7 to 5.25V ; Vss = 0V; all Digital Circuit Referenced to VSS ; TOP = -25 to +85 C, CL = 150 pF)
PARAMETER SSP Clock Frequency Clock Duty Cycle of SSP SSP Enable Timing SSP Rx Valid Timing Output Delay Time for SSP Tx Valid Output Delay Time for SSP Tx High Impedance SSP Disable Timing
SYM. TSSPC DSSP TENC TCEN TRVB TRVA TDVC TDHC TCDI TDIC
CONDITIONS SSP CLK SSP CLK SSPEN to SSP CLK SSP CLK to SSP EN Setup Time Hold Time SSP CLK to SSP Tx SSP En Rising to SSP Tx SSP CLK to SSP EN SSP EN to SSP CLK
MIN. --40 50 50 50 50 ----50 50
TYP. -- 50 -----------------
MAX. 2.048 60 --------140 140 -----
UNIT MHz % nS nS nS nS nS
Note: The parameters are shown in Figure 9-3.
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Publication Release Date: August 1997 Revision A1
W9320
10. APPLICATION INFORMATION
10.1. Handset Application for Wireless Communication
For wireless handset applications, VEXT is supplied from a 2.7 to 5.25 volt battery power supply. Meanwhile the VDD pin, connected with a 1.0 F capacitor to ground, is a 5 volt output and should not be connected to VEXT. The VDSP pin, connected with a 0.1 F capacitor to ground, is a 3 volt output. The VDD and VDSP pins should not be used to supply any external systems. The chip must also enable the charge pump by clearing the BR0[b2] of SSP port. The output power amplifier pins PO- and PO+ drive the receiver speaker. A ringer is driven by the differential power amplifier outputs AXO- and AXO+. The input to the transmitter amplifier is from a microphone output. The application circuit, Figure 10-1 is as follows.
Battery Power 1K ADPCM Chip Microphone 1K 1.0 uF 1K 20 K TG TITI+ 1.0 uF 1K 20 K VAG 0.1 uF RO AXOAXO+ Battery Power VDSP 0.1 uF VEXT 0.1 uF PI 3K Receiver Speaker 150 POPO+ PDI/RESET SSP En 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VDD 1.0 uF FSR BCLKR DR C1+ C1Vss MCLK (SCP) DT BCLKT FST SSP Rx SSP Tx SSP CLK Micro-Controller
System Clock= 10.24/16.384 MHz
ADPCM Data Input 0.1 uF
150 Ringer Speaker
20 K
ADPCM Data Output 2048 KHz Data Rate 8 KHz Frame Sync. Input
Figure 10-1 Typical Handset Application
10.2. Transformer Application for Public Switching Telephone Network (PSTN)
For this application, VEXT = +5V 5%, VDD is an input and should be connected to VEXT externally. The charge pump capacitor C1+ and C1- should not be used and the device must disable the charge pump circuit by setting BR0[b2]. Here VEXT and VDD can share the same 0.1 F capacitor. The transmitter TI-, TI+ and the receiver PO-, PO+ are connected to the secondary terminal of the telephone line transformer. The application circuit, Figure 10-2 is as follows.
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W9320
Battery Power
ADPCM Chip 10 K 10 K TG TITI+ VAG
0.1 uF
1 2 3 4 5 6 7 8 9 10 11 12 13 14
28 27 26 25 24 23 22 21 20 19 18 17 16 15
VDD FSR BCLKR DR C1+ C1Vss MCLK (SCP) DT BCLKT FST SSP Rx SSP Tx SSP CLK Micro-Controller
System Clock= 10.24/16.384 MHz
ADPCM Data Input N.C. N.C.
RO 20 K N.C. N.C.
0.1 uF
AXOAXO+ VDSP VEXT PI
0.1 uF 150
N = 0.5
ADPCM Data Output 2048 KHz Data Rate 8 K Hz Frame Sync. Input
3K
R0 = 600 Tip N=1 Ring
POPO+ PDI/RESET SSP En
Figure 10-2 Typical Transformer Application
11. HOW TO PROGRAM THE TONE GENERATOR
11.1 Introduction
The chip can enable the tone generator by setting BR7(b3) to logic "1". Under this operation, the ADPCM decoder will be disabled. The tone generator is implemented by the DSP engine based on the function "c" os(nx)". The procedure for programming the W9320 tone generator is as follows. Setting BR7(b3) to logic "1" turns on the tone generator. In addition, BR7(b1:b0) must be set to logic "0" to avoid turning on tone1 or tone2, without first programming the coefficients for freqency and attenuation. Setup the 12-bit coefficients for freqency and attenuation. First the 8 least significant bits(LSB) of 12bit coefficients must be written into BR4(b7:b0); then the 4 most significant bits(MSB) of 12-bit coefficients and address parameter will be written into BR5(b3:b0) and BR5(b7:b6) simultaneously in the same cycle. The cycle of setup coefficients is once every FSR cycle (125 S) because the DSP engine in device can access the SSP register only at every FSR cycle when the 12-bit coefficient in written into SSP refister. Poll BR7(b7) until BR7(b7) becomes a logic "0" before writing another 12-bit coefficent for BR4 and BR5. Set BR7(b1:b0) to logic "1" selects the tone 1 or tone2 generator. Publication Release Date: August 1997 Revision A1
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W9320
11.2 Tone Frequency Coefficient Calculation
The tone frequency coefficient is calculated by the function "cos(2*PI*f/8000 radian)" where PI = 3.14159, and f is frequency (Hz). The number will then be converted into a 12-bit coefficient whose MSB is the sign and whose remaining 11 bits are the fractional part found by multiplying by 2048 and rounding off the number. For example, if the frequency is 1209 Hz, the frequency number is as followed. Cos (2*3.14159*1209/8000) = 0.582053 The converted binary number is 010010101000 and the hex number 4A8, where BR4 = 4 and BR5 = A8.
11.3 Tone Attenuation Coefficient Calculation
The tone attenuation coefficient is calculated by the function "x/1.13 Vp" where x is the amplitude (Vp). The number will be converted into a 12-bit coefficient whose MSB is the sign and whose remaining 11 bits are the fractional part, found by multiplying by 2048 and rounding off the number. For example, if the attenuation is -14 dBm (600 ) Hz, first change the dBm units into Vp format as follows. sqrt[10*exp(-14/10)*600*0.001] * sqrt(2) = 0.218570 Vp The attenuation is "0.218570/1.13 = 0.193425" the binary number is 000110001100 and the hex number is 18C where BR4 = 1 and BR5 = 8C.
11.4 Frequency Coefficients for the DTMF Signal
Table 11-1 shows the 12-bit frequency coefficients for the DTMF signal. The 8 least significant bits are stored in BR4(b7:b0), the 4 most significant bits are stored in BR5(b3:b0). Table 11-2 illustrates the 12-bit attenuation coefficients for the DTMF signal such as -9 dBm (600 ) or -6 dBm (600 ) for column tone and -11 dBm (600 ) or -8 dBm (600 ) for row tone.
FREQENCY (HZ) 697 770 852 941 1209 1336 1477 1633 BR5 (HEX) 6 6 6 5 4 3 3 2 BR4 (HEX) D5 95 46 EA A8 FC 32 46
Table 11-1 Frequency Coefficients for the DTMF Signal
ATTENUATION (DBM@600 ) -11 -9 -8 -6
PEAK VALUE (VP) 0.308738 0.388679 0.436105 0.549023
BR5 (HEX) 2 2 3 3
BR4 (HEX) 30 C0 16 E3
Table 11-2 Attenuation Coefficients for the DTMF Signal
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W9320
12. PACKAGE DIMENSIONS
28 15
E
HE
1 b D
14
e1
C
A2 A
q S
A1
L
LE
e
Figure12-1 28-Lead Plastic SOP Package
There are two packages for the W9320. One is a 28-lead plastic SOP shown in Figure 12-1, the other is a 28-lead plastic DIP shown in 12-2.
SYMBOL A A1 A2 b c D E e e1 HE L LE S DIMENSION IN INCH 0.110 Max. 0.004 Min. 0.093 0.005 0.016 +0.004 -0.002 0.010 +0.004 -0.002 0.705 TYP. (0.725 Max.) 0.295 0.005 0.050 0.006 0.370 Nom. 0.406 0.012 0.036 0.006 0.055 0.006 0.043 Max. 0-10 degree DIMENSION IN MM 2.794 Max. 0.102 Min. 2.362 0.127 0.406 +0.102 -0.051 0.254 +0.102 -0.051 17.90 TYP. (18.415 Max.) 7.493 0.127 1.270 0.152 9.396 Nom. 10.312 0.305 0.914 0.203 1.397 0.203 0.102 Max. 0-10 degree
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Publication Release Date: August 1997 Revision A1
W9320
D
28 15
E1
1
14
S A A2 L B B1 e1 A1 Base Plane Seating Plane a
E c
eA
Figure12-2 28-Lead Plastic DIP Package
SYMBOL A A1 A2 B
DIMENSION IN INCH 0.210 Max. 0.010 Min. 0.155 0.005 0.018 +0.004 -0.002
DIMENSION IN MM 5.334 Max. 0.254 Min. 3.937 0.127 0.457 + 0.102 - 0.051 1.524 +0.102 -0.051 0.254 +0.102 -0.051 37.084 TYP. (37.33 Max.) 15.24 0.254 13.843 0.127 2.540 0.254 3.302 0.254 16.51 0.508 2.286 Max. 0-15 degree
B1
0.06 + 0.004 - 0.002
C
0.01 + 0.004 - 0.002
D E E1 e1 L eA S a
1.46 TYP. (1.47 Max.) 0.6 0.01 0.545 0.005 0.100 0.01 0.130 0.01 0.650 0.02 0.09 Max. 0-15 degree
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W9320
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5792697 http://www.winbond.com.tw/ Voice & Fax-on-demand: 886-2-7197006
Winbond Electronics (H.K.) Ltd.
Rm. 803, World Trade Square, Tower II, 123 Hoi Bun Rd., Kwun Tong, Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Winbond Electronics North America Corp. Winbond Memory Lab. Winbond Microelectronics Corp. Winbond Systems Lab.
2730 Orchard Parkway, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-9436668
Taipei Office
11F, No. 115, Sec. 3, Min-Sheng East Rd., Taipei, Taiwan TEL: 886-2-7190505 FAX: 886-2-7197502
Note: All data and specifications are subject to change without notice.
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Publication Release Date: August 1997 Revision A1

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